VLSI Design Engineer

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Jenene Sailor

jenene.sailor@gmail.com | (355) 518-6216 | Portland, ME


As a VLSI design engineer with over 4 years of experience, I have gained a strong understanding of the various aspects of chip design and verification. My expertise lies in using industry-standard tools for RTL coding, logic synthesis, static timing analysis, Place & Route (P&R), and signal integrity analysis. In addition to this, I am also well-versed in working with Verilog/VHDL simulators such as Modelsim and QuestaSim. Over the course of my career, I have designed several complex chips that are currently being used in consumer electronics devices.


VLSI Design Engineer at Analog Devices, Inc., MEMar 2022 - Present

  • Led the design and implementation of a new generation of VLSI chips that increased performance by 25% while reducing power consumption by 50%.
  • Developed an innovative process for designing custom VLSI circuits that reduced development time from 6 months to 2 weeks.
  • Implemented a new testing methodology for VLSI circuits that improved yield rates from 80% to 97%.
  • Designed and implemented several complex VLSI systems, including a 4-million gate chip with over 100 million transistors.
  • Authored or co-authored numerous papers onV.

VLSI Design Engineer II at Integrated Device Technology, Inc., MEAug 2018 - Jan 2022

  • Defined and designed an 8-bit microprocessor with a clock speed of 2.4 GHz, which improved the processing speed by 12% compared to the previous design.
  • Implemented a new cache memory hierarchy that reduced access time by 20% and increased data throughput by 25%.
  • Developed novel techniques for power reduction in digital circuits that helped save 10% on overall power consumption.
  • Led the team in designing & validating high-speed memories (SRAM/DDR) interface IPs used in next generation SoCs. This work resulted in 4 patents being filed.
  • Completed layout for 7nm FinFET technology node, meeting all timing closure requirements while achieving desired area targets set initially.


Bachelor of Science in Electrical Engineering at University of Maine, Orono, MEAug 2014 - May 2018

I've learned how to design, test, and deploy electrical and electronic devices and systems.


  • VLSI design
  • Verilog or VHDL
  • CAD tools (e.g., Cadence, Synopsys)
  • Logic synthesis (e.g., Synopsys Design Compiler)
  • Static timing analysis (STA)
  • Physical verification and simulation tools (e.g., Mentor Graphics Calibre/QuestaSim)
  • Layout editors and place-and-route systems

Carmella Juby

carmella.juby@gmail.com | (116) 448-6522 | Wichita, KS


I am a VLSI Design Engineer with over 4 years of experience in the semiconductor industry. I have worked on several design projects involving ASICs, FPGAs, and full-custom chips. My work has involved both digital and analog circuit design, layout verification, timing closure, signal integrity analysis, power optimization, and static timing analysis. I am also experienced in using Verilog HDL for RTL coding and simulation. In addition to my technical skills, I have strong communication and interpersonal skills that allow me to work effectively as part of a team.


VLSI Design Engineer at Integrated Device Technology, KSMar 2022 - Present

  • Led the design and development of a new generation VLSI chip that achieved 50% reduction in power consumption while providing 25% performance improvement over the previous generation.
  • Defined micro-architecture, RTL coding, timing closure & verification for state of the art high speed SerDes interface IPs targeting 28Gbps data rate with 7nm process technology.
  • Implemented novel techniques to achieve 20% area reduction and 30% performance gain for an AI accelerator engine used in autonomous vehicles applications. The design was taped out successfully in 16nm FinFET process.
  • Achieved first pass silicon success for multiple tape outs across various technologies (28nm – 7nm) by taking complete ownership from netlist to GDS delivery including sign off.

VLSI Design Engineer II at Maxim Integrated, KSJul 2018 - Mar 2022

  • Successfully designed and implemented a new VLSI design that improved performance by 15%.
  • Successfully completed all project deliverables on time and within budget.
  • Managed a team of 5 engineers in the successful completion of a complex VLSI design project.
  • Successfully reduced manufacturing costs by 10% through process improvements.
  • Achieved first pass success rate of 95% for designs managed during Q2 2016.


Bachelor of Science in Electrical Engineering at Kansas State University, KSAug 2014 - May 2018

I've learned how to design, build, and test electrical circuits and systems.


  • VLSI
  • Verilog
  • VHDL
  • FPGA
  • Quartus Prime
  • ModelSim